近日，韩国国立釜庆大学的Youngsun Han及其研究团队取得一项新进展。经过不懈努力，他们提出用于增强基于格子手术表面编码的鲁棒混合量子比特平面架构。相关研究成果已于2024年2月29日在国际知名学术期刊《物理评论A》上发表。

该研究团队提出了一种称为Qentaurus的旋转和非旋转表面代码的量子比特平面架构，该架构结合了逻辑量子比特的各种码距，在保持量子比特效率的同时实现鲁棒纠错。Qentaurus被设计为在计算、布局和码距方面具有高度可扩展性。研究人员使用距离-3和-7代码的Qentaurus进行了一个案例研究，以评估性能。此外，研究人员还开发了一种考虑量子电路关键路径的量子比特放置方案，以降低逻辑错误率和门数。

实验结果表明，与距离-3棋盘架构相比，Qentaurus显著降低了整体逻辑错误率(平均降低15.76%，最高可达25.25%)。在额外实施量子比特放置方案后，平均降幅增加到13.44%(最高为39.07%)。值得注意的是，Qentaurus-3&7保持了与距离-5棋盘相当的逻辑错误率，实现了相当高的量子比特效率。距离-5棋盘比距离-3棋盘多需要227.7%的物理量子比特，而Qentaurus-3&7只需要距离-3棋盘所需的131.2%的物理量子比特，这标志着资源间隙大幅减少了96.5%。

单独使用Qentaurus时，总门数平均减少了1.74%，使用量子比特放置方案时平均减少了3.33%。研究人员认为，该研究所提出的Qentaurus和量子比特放置方案，有可能在实际应用中显著提高大规模量子计算机的纠错性能。

据悉，量子计算以其前所未有的速度和能力为解决复杂问题提供了新途径，但与此同时，其对错误的敏感性使得纠错代码成为关键。在评估纠错代码性能时，一个核心指标是码距，它反映了代码能够纠正的错误数量。目前，量子比特平面架构采用相同的码距策略。值得注意的是，虽然增大码距可以降低逻辑错误率，但这需要更多的资源投入。举例来说，与距离-3代码相比，距离-5代码在提供更高逻辑错误弹性的同时，也消耗了更多的资源。

附：英文原文

Title: Robust hybrid qubit plane architecture for enhancing lattice-surgery-based surface codes

Author: Sengthai Heng, Sovanmonynuth Heng, Dongmin Kim, Youngsun Han

Issue&Volume: 2024/02/29

Abstract: Quantum computing offers unprecedented speed and power for solving complex problems, but its susceptibility to errors makes error-correction codes crucial. An important metric for evaluating the performance of error-correction codes is the code distance, which measures the number of errors a code can correct. Current qubit-plane architectures are implemented using the same code distance. However, a larger code distance reduces the logical error rate but increases resources. In fact, distance-5 code uses more resources but offers higher resilience to logical errors compared to distance-3 code. We propose a qubit-plane architecture for rotated and unrotated surface codes called Qentaurus that combines various code distances of logical qubits for robust error correction while maintaining qubit efficiency. Qentaurus is designed to be highly scalable regarding computation, layout, and code distance. We performed a case study using Qentaurus with distance-3 and -7 codes to evaluate the performance. Moreover, we additionally developed a qubit placement scheme that considers the critical path of the quantum circuit to reduce the logical error rate and gate count. Our main experimental results demonstrated that Qentaurus considerably reduces the overall logical error rate (by 15.76% on average and up to 25.25%) than that of the Distance-3 Checkerboard architecture. After additionally implementing the qubit placement scheme, the average reduction increases to 13.44% (up to 39.07%). Notably, the Qentaurus-3&7 maintains logical error rates comparable to those of the Distance-5 Checkerboard, achieving considerable qubit efficiency. The Distance-5 Checkerboard demands 227.7% more physical qubits than that required by the Distance-3 Checkerboard, while Qentaurus-3&7 utilizes just 131.2% of the physical qubits required by Distance-3 the Checkerboard, marking a substantial reduction of 96.5% in the resource gap. The overall gate count is reduced by an average of 1.74% with Qentaurus alone and by 3.33% on average with the qubit placement scheme. We believe that the proposed Qentaurus and qubit placement scheme have the potential to significantly improve the error-correction performance of large-scale quantum computers in practical applications.

DOI: 10.1103/PhysRevA.109.022440

Source: https://journals.aps.org/pra/abstract/10.1103/PhysRevA.109.022440